Phase locked loop circuit

ABSTRACT

A frequency synthesized receiver utilizes, as a local oscillator, a phase-locked circuit formed of a reference signal oscillator, a voltage controlled oscillator, a programmable divider, a phase comparator, and a low-pass filter. For tuning to a desired frequency, the dividing ratio of the programmable divider is controlled by an up/down counter connected in parallel with a shift register. The latter is supplied with a clock pulse signal and a binary coded selecting signal furnished from a micro computer. The selecting signal corresponds to a desired broadcast frequency. The up/down counter is caused by the micro computer to count up or down from the count value stored in the shift register, thereby causing the received frequency to rapidly sweep, at predetermined steps of, for example, 100 KHz.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a PLL (phase-locked loop)frequency synthesized receiver and is directed more particularly to aPLL frequency synthesized receiver which can shorten an up/downbroadcast station selection time.

2. Description of the Prior Art

There are presently known frequency-synthesized receivers which use aphase-locked loop (PLL) circuit as a local oscillator circuit. The PLLcircuit normally includes a programmable frequency divider whosedividing ratio determines the local oscillation frequency. In such areceiver, a station selection code is provided to correspond to adesired received frequency. This code is stored or generated in acontrol apparatus, which can be a microcomputer, and is supplied to adata register coupled with the programmable divider. The contents of thedata register then determine the dividing ratio of the programmabledivider to determine the local oscillator frequency and, hence, todetermine the received frequency.

If it is desired to change the tuning of the receiver by continuouslysweeping the local oscillation frequency up or down, the contents of thedata register must be changed by unit steps to correspond, for example,to frequency changes of 100 KHz.

Unfortunately, each up or down step requires a rather involved operationand consumes an inordinate amount of time. This prevents the receiverfrom changing frequencies rapidly.

For example, to change the frequency by one increment of 100 KHz (i.e.,to change the dividing ratio of the programmable divider by "1") thecode stored in the control apparatus, which code has been converted to a16-bit BCD signal to control the contents of the data register, isconverted back to binary form, and then is incremented or decremented.Then the incremented or decremented code is converted again to a BCDsignal and is transferred to the data register. As the code can behandled only on a bit-by-bit basis, this operation consumes a great dealof time. In the case of a received frequency change from one end of thefrequency band to the other, this operation can be annoyingly long.

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide afrequency synthesized receiver free from the defects encountered inprior art receivers.

Another object of the invention is to provide a frequency synthesizedreceiver in which the frequency dividing ratio of a programmable dividerin a PLL circuit can be quickly varied up or down by an up/down counterand a shift register coupled to each other to shorten the broadcaststation selecting time.

In accordance with one embodiment of the present invention, a PLLcircuit is provided which can serve as the local oscillator circuit of afrequency-synthesized receiver. Such as PLL circuit comprises areference signal oscillator, a voltage controlled oscillator (VCO)providing an output oscillation signal whose frequency depends on anerror signal applied thereto, a programmable divider connected to theVCO to divide down the output oscillating signal by a programmeddividing ratio, a phase comparator providing the error signal inaccordance with the phase difference between the divided-down outputsignal and the output of the reference signal oscillator, and a dataregister supplied with a clock pulse signal and a selection signal,while can be a binary coded signal to produce a programming controlsignal to establish the dividing ratio of the programmable divider. Anup/down counter is interposed between the data register and theprogrammable divider to latch the programming control signal therein andto selectively increment the same upwardly or downwardly to control thedividing ratio of the programmable divider.

Still other objects, features and advantages of the present inventionwill be apparent from the following descriptions taken in conjunctionwith the attached drawings throughout which like reference charactersidentify the same elements and parts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a prior art synthesized receiver.

FIG. 2 is a front view showing the front panel of a PLL synthesizedreceiver to which this invention is favorably applied;

FIG. 3 is a block diagram showing an example of a frequency synthesizedreceiver that includes a local oscillator circuit embodying thisinvention;

FIGS. 4A to 4E are time charts used to explain the operation of theexample shown in FIG. 3; and

FIG. 5 is a schematic circuit diagram showing a practical example of apart of the embodiment of the invention shown in FIG. 3.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

For background and to emphasize the advantages of this invention, aprior art frequency synthesized receiver is shown in FIG. 1. In thisreceiver, an antenna 1 receives a broadcast RF signal and then suppliesthe same through an RF (radio frequency) amplifier 2 to one input of amixer circuit 3. Another input thereof is supplied with a localoscillation signal LO from a phase-locked loop local oscillator circuit4. A voltage controlled variable frequency oscillator (VCO) 4a thereofgenerates the local oscillation signal LO. The output signal from themixer circuit 3 is supplied as an IF (intermediate frequency) signal toan IF amplifier 5, and thence to a detector circuit 6. An audio signalis obtained at the output side of the detector circuit 6 and is fed to alow frequency or audio amplifier 7, and the output signal therefrom isfed to an audio transducer 8 to provide audio sound.

The local oscillation signal LO from the PLL local oscillator circuit 4is also applied to a first frequency divider, i.e., a pre-scaler 4b,which frequency-divides the signal LO by 100. The divided signaltherefrom is applied to a programmable frequency divider 4c. Thefrequency dividing ratio of the programmable divider 4c is controlled inresponse to the selection of the desired broadcast station frequency bymeans of a station selection code applied thereto from a data register9. The latter normally consists of a shift register and a latch circuit.The divided-down output signal from the programmable divider 4c isapplied to a phase comparator 4d at one input terminal thereof and areference oscillator 4e provides a reference frequency signal to anotherinput terminal thereof. The phase comparator 4d produces an errorvoltage corresponding to the phase difference between the above twosignals. The output signal from the phase comparator 4d is suppliedthrough a low-pass filter 4f to the local oscillator 4a and the filterederror signal controls the VCO 4a. Thus, the latter produces the localoscillation signal LO as a stable oscillating signal whose frequency isa function only of the frequency dividing ratio of the programmabledivider 4c.

As better shown in FIG. 2, an operation or control key assembly 10consists of ten numerical keys 10a, an up-scan key 10b, a down-scan key10c, preset selection keys 10d for reading out selection signalscorresponding to the broadcast stations previously preset in a memory(not shown), as well as other keys for selecting various functions. Acontrol apparatus 11, here constituted by a microcomputer and associatedperipheral devices, supplies a clock signal to a clock signal inputterminal 9a of the data register 9, supplies the broadcast stationselection signal, in response to the operation of the control key 10, toa data input terminal 9b of the data register 9, and furnishes a latchsignal to a latch signal input terminal 9c of the data register 9. Thecontrol apparatus 11 also supplies a display signal to a frequencydisplay device 12 on which the received frequency and other parametersof interest are displayed.

With the prior-art frequency synthesized receiver constructed as shownin FIG. 1, a preset selection operation is carried out by depressing aselected one of the preset keys 10d corresponding to the desiredbroadcast station so that a station control signal corresponding to thedesired broadcast station frequency is fetched out of memory. Then thecontrol apparatus 11 applies the station selection signal, which can bea BCD (binary coded decimal) signal consisting of four four-bit words(i.e., 16 bits), which is in synchronism with the clock signal, to thedata register 9. The shift register of data register 9 temporarilystores the station selection signal. Thereafter, this station selectionsignal is transferred to the latch circuit of the data register 9 inresponse to the latch signal applied thereto from the control apparatus11. Then, the station selection signal is fed to the programmabledivider 4c in the PLL local oscillator circuit 5 to set its frequencydividing ratio to correspond to the station selection signal.Consequently, the VCO 4a provides the local oscillation signal LO at theappropriate frequency to receive the desired broadcast station.

If the receiving frequency is sequentially varied by increments of, forexample, 100 KHz (corresponding to unit increments in the dividing ratioof the programmable divider 4c) to achieve an upward or downwardcontinuous station selection operation, a BCD signal of 16 bits isapplied from the control apparatus 11 to the register 9. Generally, thefirst 12 bits are the data for controlling the frequency dividing ratioof the programmable divider 4c (corresponding to three significantdecimal of the frequency) and the remaining 4 bits are the data forchanging over the comparing frequency and the input signal. This 16-bitsignal is temporarily stored in the shift register of the data register9 in synchronism with the above-mentioned clock signal and then islatched by the above-mentioned latch signal which is applied to the dataregister 9 after 16 clock signals. Thus, a time of 17 clock signals isrequired for each step of 100 KHz. If a clock signal period of 2 μsec isassumed, this corresponds to 34 82 sec for each step, and the stationselection time can become rather long.

Further, when the up/down control of the control apparatus(micro-computer) 11 is carried out by means of BCD signals, aBCD-to-binary conversion becomes necessary, which results in additionallengthening of station selection time.

As described above, with the prior art synthesized receiver shown inFIG. 1, if the receiving frequency is successively incremented by stepsof, for example, 100 KHz to continuously carry out an upward or downwardstation selection operation, it is necessary that at every time that thereceiving frequency is incremented by one step, the receiving frequencyis converted into a binary code to correspond to a revised stationselection signal, this revised station selection signal, in binary code,is stored in the data register 9, and then the station selection signalis fed as a binary code from the data register 9 to the programmabledivider 4c to change the frequency dividing ratio thereof by a step thatcan, for example, be "1." This continuous station selection operationconsumes an unduly long time. Consequently, station selection can not becarried out rapidly.

Turning now to FIG. 3, an example of the frequency synthesized receiverembodying a phase-locked loop circuit according to the present inventionwill now be described. In FIG. 3, the parts and elements correspondingto those of FIG. 1 are identified with the same reference numerals and adetailed description thereof is omitted.

The broadcast station selection signal and clock signal are suppliedfrom the control apparatus 11 to a shift register 9', and an up/downchange-over signal is also fed from the control apparatus 11 to anup/down control circuit 13 through a change-over signal input terminal13a thereof. The control apparatus 11 is here shown as a micro-computer.The up/down control circuit 13 has a first output terminal 13b whichsupplies an up/down control signal to an up/down control signal inputterminal 14b of an up/down counter 14 to set it into an up or a downstate. A second output terminal 13c of the up/down control circuit 13supplies a first gate signal to a gate signal input terminal 9g of theshift register 9', and a third output terminal 13d thereof supplies asecond gate signal to one input terminal 15a of an OR circuit 15 whichis supplied at its other input terminal 15b with the latch signal fromthe control apparatus 11. The output signal from the OR circuit 15 isfed, as a gate signal, to a gate signal input terminal 14g of theup/down counter 14. In this case, when the gate signal is supplied fromthe second output terminal of the up/down control circuit 13 to the gatesignal input terminal 9g of the shift register 9', the counted contentof the up/down counter is transferred without change to the shiftregister 9'. Further, when the second gate signal from the third outputterminal of the up/down control circuit 13 is fed to the input terminal15a of the OR circuit 15 or the latch signal from the control apparatus11 is fed to the other input terminal 15b of the OR circuit 15 so thatthe gate signal from the output terminal of the OR circuit is fed to thegate signal input terminal 14g of the up/down counter 14, the storedcontent in the shift register 9' is transferred without change to theup/down counter 14. The control apparatus 11 supplies a clock signal toa clock signal input terminal 14a of the up/down counter 14 to cause itto count up or down, as appropriate. The signal applied to the up/downcontrol signal input terminal 14b controls the counting direction to beup or down. Then, the counted contents obtained at the respective outputterminals of the up/down counter 14 are supplied as the stationselection signals to the programmable divider 4c to control itsfrequency dividing ratio according to the counted contents. Theremaining construction of the example of FIG. 3 is substantially thesame as that of the prior art example shown in FIG. 1.

According to the present invention constructed as above, when thestation selection signal corresponding to a desired broadcast station isread out from the stored station selection signals, which are previouslypreset in the memory in correspondence with the desired broadcaststations, to receive one of the desired broadcast stations, one of thepreset selection keys 10d corresponding to the desired broadcast stationis actuated to supply the signal to the control apparatus 11. Then, thecontrol apparatus 11 supplies the clock signal to the shift register 9'which is also furnished with the station selection signal correspondingto the desired broadcast station and is supplied from the memory. Thus,the station selection signal is temporarily stored in the shift register9'. Thereafter, the latch signal is fed from the control apparatus 11 tothe OR circuit 15 through its input terminal 15b to transfer the stationselection signal stored in the shift register 9', without modification,to the up/down counter 14. The station selection signals appearing atthe respective output terminals of the up/down counter 14 are applied tothe programmable divider 4c in the PLL circuit 4 to make its frequencydividing ratio appropriate to correspond to the station selectionsignal. Then, the oscillation frequency of the local oscillation signalLO from the VCO 4a is varied to receive the desired broadcast station.

The receiving frequency can be sequentially increased or decreased bysteps 100 of KHz to carry out a continuous station selecting operation.When it is desired to change the direction of scan of the stationselection operation from the up-scan made to the down-scan mode (or fromthe down-scan to the up-scan mode), the up-scan key 10b (or down-scankey 10c) shown in FIG. 2 is actuated to supply the respective signal tothe control apparatus 11. Then, a change-over signal (FIG. 4A) forchanging over the scan direction from the up-scan to the down-scan mode(or from the down-scan to the up-scan mode) is supplied at a time t₁from the control apparatus 11 to the change-over signal input terminal13a of the up/down control circuit 13. At a subsequent time t₂, thefirst gate signal shown in FIG. 4B is supplied from the second outputterminal of the up/down control circuit 13 to the gate signal inputterminal 9g of the shift register 9' to transfer the counted content ofthe up/down counter 14 to the shift register 9'. Further, at a next timet₃, the up (or down) control signal shown in FIG. 4C is supplied fromthe first output terminal of the up/down control circuit 13 to thecontrol signal input terminal 14b of the up/down counter 14 to set thesame to the up-scan (or down-scan) mode. At the same time, the secondgate signal shown in FIG. 4D is supplied from the third output terminalof the up/down control circuit 13 to the input terminal 15a of the ORcircuit 15 which in turn supplies the gate signal to the gate signalinput terminal 14b of the up/down counter 14. As a result, the contentsof the shift register 9' are transferred to the up/down counter 14. At asubsequent time t₄, the clock signal shown in FIG. 4E is supplied fromthe control apparatus 11 to the clock signal input terminal 14a of theup/down counter 14 to increase or decrease its counted contentssuccessively by, for example, "1." This results in a successive 100 KHzchange in signal LO, and a similar change in the received stationfrequency. Accordingly, the programmable divider 4c of the PLL circuit 4is supplied from the output terminals of the up/down counter 14 withappropriate station selection signals to successively change thereceiving frequencies by steps of 100 KHz. Thus, the frequency dividingratio of the programmable divider 4c is varied successively and theoscillation frequency of the local oscillation signal LO is successivelyvaried to achieve the continuous station selection operation.

In the case that the selection operation is repeated from the up-scan tothe up-scan mode (or from the down-scan to the down-scan mode), theup/down change-over signal shown in FIG. 4A is not supplied at the timet₁ from the control apparatus 11 to the change-over signal inputterminal 13a of the up/down control circuit 13. Thus, at the times t₂and t₃ the counted contents of the up/down converter 14, controlled bythe output signal from the up/down control circuit 13, is nottransferred to the shift register 9' and the state of the up/downcounter 14 is not changed to transfer the content of shift register 9'to the up/down counter 14. As a result, from the time t₄ the clocksignal shown in FIG. 4E is continuously fed from the control apparatus11 to the clock signal input terminal 14a of the up/down counter 14 tosuccessively and rapidly increase or decrease its counted content.

As described above, according to the present invention, the up/downcounter 14 is interposed between the shift register 9' and theprogrammable divider 4c of the PLL local oscillator circuit 4, and thestation selection signal, which controls the frequency dividing ratio ofthe programmable divider 4c, is fed thereto from the up/down counter 14.Therefore, when the receiving frequency is successively varied up ordown by the step of, for example, 100 KHz to carry out a continuousstation selection operation, such operation can be performed rapidly byincreasing or decreasing only the counted contents of the up/downcounter 14.

Further, according to this embodiment of the present invention, thecounted contents of the up/down counter 14 is transferred withoutmodification to the shift register 9' in accordance with the up/downchangeover signal applied to the input terminal 13a of the up/downcontrol circuit 13 from the control apparatus 11. As a result, if acheck terminal 9d, used to check the data stored in the shift register9', is provided on the shift register 9', the counted contents of theshift register 9' can be obtained from the check terminal 9d at anytime, and the present counted contents in the up/down counter 14 can beused to generate a display of the received frequency. Further, sinceaccording to this invention it becomes unnecessary to store the increaseand decrease of the counted contents at every step, the data storagespace in the control apparatus 11 can be kept to a minimum or saved forother functions.

Throughout this discussion the term "incrementing" is used generally tocover both counting up and counting down.

A practical example of the shift register 9', the up/down controlcircuit 13 and the up/down counter 14 of the frequency synthesizedreceiver according to the invention is disclosed in FIG. 5, in which theparts corresponding to those of FIG. 3 are identified with the samereference numerals and a detailed description thereof is omitted.

In FIG. 5, A₁, A₂, A₃, . . . A_(i) are T-type (trigger-type) flip-flopcircuits which form the up/down counter 14; B₂, B₂, B₃, . . . B_(i) areD-type flip-flop circuits which form the shift register 9'; and C₁, C₂,C₃, and C₄ are D-type flip-flop circuits which form the up/down controlcircuit 13. The clock signal input terminal 16 is coupled to each of theD-type flip-flop circuits C₁ to C₄, and the clock signal input terminal9a is coupled to each of the D-type flip-flop circuits A₁ to A_(i).

While one embodiment of this invention is illustrated hereabove, it willbe apparent that many modifications and variations could be effectedtherein by one skilled in the art without departing from the spirit orscope of the present invention, which is to be measured by the appendedclaims.

We claim as our invention:
 1. A phase-locked loop circuitcomprising:reference signal oscillator means providing a referenceoscillating signal; voltage controlled oscillator means having an outputproviding an output oscillating signal whose frequency depends on anerror signal applied thereto; programmable divider means connected tothe output of said voltage controlled oscillator means for providing adivided-down signal, having a programmable dividing ratio and having acontrol terminal for receiving a programming control signal forprogramming the dividing ratio thereof; phase comparator means suppliedwith said reference oscillating signal and said divided-down signal andan output providing said error signal in response to the phasedifference therebetween; data register means supplied with a clock pulsesignal and a selection signal in synchronism with the clock pulse signalfor providing said programming control signal from an output thereof;and up/down counter means coupled between the output of said dataregister means and the control terminal of said programmable dividermeans to latch the programming control signal therein, and toselectively increment the same to control the dividing ratio of saidprogrammable divider means.
 2. A phase-locked loop circuit according toclaim 1, in which said clock pulse signal and said selecting signal aresupplied from a micro-computer to said data register means.
 3. Aphase-locked loop circuit according to claim 1, further comprisingup/down control circuit means to control the direction of counting ofsaid up/down counter means and to coordinate the operation of the latterwith that of said register means.
 4. A phase-locked loop circuitaccording to claim 3, in which said up/down control circuit means issupplied with an up/down change-over signal and in response theretoproduces a first control signal supplied to said up/down counter meansto control the counting direction thereof and to condition the same toincrement the count value thereof in response to a further clock pulsesignal; a second control signal supplied to said data register means totransfer the programming control signal contained in said up/downcounter means to said data register means; and a third control signalsupplied to said up/down counter means to transfer the programmingcontrol signal stored in said data register means to said up/downcounter means.
 5. A phase-locked loop circuit according to claim 4, inwhich said first control signal is delayed for a predetermined time withrespect to said second control signal so that said up/down counter meansis changed over from one of an up-counting mode and a down-counting modeto the other thereof after the programming control signal contained insaid up/down counter means is transferred to said data register meansand before the counting operation thereof is started in response to saidfurther clock pulse signal.
 6. A phase-locked loop circuit according toclaim 4; in which said data register means includes a data checkterminal providing the contents of said data register means.
 7. Aphase-locked loop circuit according to claim 6; further comprisingdisplay means coupled to said data clock terminal for displaying a valuecorresponding to the contents of said data register means.
 8. Aphase-locked loop circuit according to claim 1; wherein said selectionsignal is provided to said data register means as a binary coded datasignal.
 9. A radio receiver comprising means for receiving a broadcastsignal, a local oscillator for providing a local oscillator signal,mixer means for mixing the received broadcast signal with said localoscillator signal to produce a IF signal, and detector means forprocessing the IF signal to produce output information, wherein saidlocal oscillator is formed of a phase-locked loop circuit includingreference oscillator means providing a reference signal; voltagecontrolled oscillator means having an output providing said localoscillator signal whose frequency depends on an error signal appliedthereto; programmable divider means coupled to the output of saidvoltage controlled oscillator means providing a divided-down version ofthe local oscillator signal at an output thereof, having a programmabledividing ratio, and having a control terminal for receiving aprogramming code for programming the dividing ratio thereof; phasecomparator means supplied with the reference signal and the divided-downversion of the local oscillator signal and providing said error signalin response to the phase difference therebetween; data register meanssupplied with a clock pulse signal and a selection signal in synchronismwith the clock pulse signal for providing said programming controlsignal from an output thereof; and up/down counter means coupled betweenthe output of said register means and the control terminal of saidprogrammable divider means to latch the programming control signaltherein and to selectively increment the same to control the dividingratio of said programmable divider means.
 10. A radio receiver accordingto claim 9; further comprising digital control apparatus for providingsaid selection signal, said clock pulse signal, and an up/down controlsignal for controlling the incrementing of the programming controlsignal by said up/down counter means.
 11. A radio receiver according toclaim 10; further comprising a control key arrangement coupled to saiddigital control apparatus to selectively establish the selection signalcorresponding to a desired frequency, and to selectively establish anup-counting state and a down-counting state wherein said up/down countermeans counts up and down, respectively.
 12. A radio receiver accordingto claim 9, wherein a unit increment of said up/down counter meanscorresponds to a frequency change of approximately 100 KHz in said localoscillator signal.